DesignCon is the premier high-speed communications and system design conference and exposition, offering industry-critical engineering education in the heart of electronics innovation — Silicon Valley.

The Must Attend Event for Chip, Board, and Systems Design Engineers

Schedule:
Tuesday, January 31, 2023
8:00am - 9:00am: Welcome Breakfast - Mission City Ballroom B1
9:00am - 11:30am: Tutorial – Bird's-Eye Viewing 200+Gbps per Lane & Beyond with Various Signal-to-Noise Ratio Metrics - Ballroom F
9:00am - 11:30am: Tutorial – Measuring PSNR/PSRR/PSMR to Meet QSFP/OSFP High-Speed Requirements - Ballroom E
9:00am - 11:30am: Tutorial – Quantum Computer (Superconductor Qubits) Hardware Design Guidelines - Ballroom D
9:00am - 4:30pm: Boot Camp – Memory Design Fundamentals: Next-Generation Memory Systems - Ballroom GH
11:45am - 12:30pm: Keynote – Post-Quantum Cryptography: The Next Decade of Cryptographic Hardware Design - Elizabeth A. Hangs Theater
12:30pm - 2:30pm: Conference Networking Lunch - Mission City Ballroom B1
2:00pm - 4:30pm: Tutorial – Design & Verification for High-Speed I/Os at 10 to 112 & 224 Gbps with Jitter, Signal Integrity, & Power Optimized - Ballroom F
2:00pm - 4:30pm: Tutorial – Machine Learning for Embedded Developers - Ballroom E
2:00pm - 4:30pm: Tutorial – PCB Design Techniques to Improve ESD Robustness - Ballroom C
2:00pm - 4:30pm: Tutorial – Stackups: The Design Within the Design - Ballroom D
4:45pm - 6:00pm: Panel – Enabling Next Generation Co-Packaging Solutions - Ballroom D
4:45pm - 6:00pm: Panel – PCIe 6.0: Challenges of Achieving 64GT/s with PAM4 in Lossy, HVM Channels - Ballroom F
4:45pm - 6:00pm: Panel – Real-World Deployment of AI/ML in Chip & Board Applications - Ballroom C
4:45pm - 6:00pm: Panel – The Case of the Closing Eyes: Bridging FEC to Signal Integrity - Ballroom GH
6:00pm - 8:00pm: Welcome Reception - Santa Clara Ballroom, Hyatt Regency Santa Clara

Wednesday, February 1, 2023
8:00am - 8:40am: Advanced Testing Challenges at 32GBaud PAM4 with PCIe 6.0 - Great America K
8:00am - 8:40am: In-Situ De-Embedding - Great America 2
8:00am - 8:45am: A Novel Simulation Flow for DDR5 Systems with Clocked Receivers - Ballroom G
8:00am - 8:45am: Enabling Industry's First Beyond 8.5Gbps/pin LPDDR5X PHY Using Rx Offset Calibration Scheme & Robust Training Method - Ballroom D
8:00am - 8:45am: High-Speed Loopback Applications by Utilizing a Differential DPDT MEMS Switch - Ballroom E
8:00am - 8:45am: New Directions in Memory Technology - Ballroom B
8:00am - 8:45am: Next Generation 224 Gbps-PAM4 Chip-to-Module Channel Design, Link Simulation, & Analysis - Ballroom H
8:00am - 8:45am: Overview of PCB Fabrication Influences on RF Performance for Millimeter-Wave Radar - Ballroom C
8:00am - 8:45am: PCIe Gen6 CEM Connector & PCB Design Optimizations - Great America J
8:00am - 8:45am: Technologies That Will Shape The Future Of The Data Center - Great America 1
8:00am - 8:45am: Towards 106 GBaud: Analysis of Latest 53 GBaud DUTs Informs the Improvements of Methodology - Ballroom F
8:55am - 9:35am: Advanced Jittter Transfer Measurements for PLL Characterization - Great America K
9:00am - 9:40am: Successful PCIe Interconnect Guidelines for 8, 16, and 32 GT/s - Great America 2
9:00am - 9:45am: Choosing The Right High-Performance Memory Solution - Great America 1
9:00am - 9:45am: Hardware Approaches to Qubits - Ballroom B
9:00am - 9:45am: How to Design Secured Power Delivery Network of Cryptographic Devices: Challenges, Evaluation Methods, & Solutions - Ballroom D
9:00am - 9:45am: Interconnect Trends & Guidance for Automotive High-Speed Applications - Great America J
9:00am - 9:45am: MIPI CPHY Modeling, Measurement & Correlation for AR/VR Devices - Ballroom E
9:00am - 9:45am: One-Phase Immersion Cooling Liquids Characterization - Ballroom H
9:00am - 9:45am: Simulation & Analysis of Electrical/Optical Communication Links Using Free Software - Ballroom G
9:00am - 9:45am: VRM Modeling & Stability Analysis for Power Integrity Engineers - Ballroom F
9:00am - 9:45am: Wiring the Future of Mobility - Ballroom C
10:00am - 11:00am: Keynote – Enabling Autonomous Robotics Through Electrical Engineering - Elizabeth A. Hangs Theater
11:10am - 11:50am: 112 Gbps PAM4 Front Panel Connectivity - Real World Implementation & Correlation - Great America 2
11:10am - 11:50am: Next Gen Development in USB4 Version 2.0 - Great America K
11:15am - 12:00pm: A New Power Integrity Requirement to Supplement Target Impedance: Quantifying PDN Impedance Flatness from Sandler NISM - Ballroom G
11:15am - 12:00pm: Best Practices for A Converged High-Speed Channel Design for Cloud Servers in Both Air-Cooling & Immersion-Cooling - Ballroom F
11:15am - 12:00pm: End-to-End Security Features Protecting Mission-Critical Data for CXL Based Platforms - Ballroom E
11:15am - 12:00pm: More Relevant Than Ever: Safety & Security for Automotive Sensing Systems - Ballroom C
11:15am - 12:00pm: OCP ORv3 Rack & Power Distribution Overview - Great America J
11:15am - 12:00pm: Optical Fiber to the Processor - Ballroom B
11:15am - 12:00pm: Package & IC Aware PCB PDN Design by Optimizing Decoupling Capacitors While Evaluating PDN Voltage Ripple Noise - Ballroom H
11:15am - 12:00pm: Panel: Automotive IP Solutions For The Software-Defined Vehicle - Great America 1
11:15am - 12:00pm: Statistical BER Analysis of Concatenated FEC in Multi-Part Links - Ballroom D
11:15am - 12:15pm: Panel – Deploying ML in EDA Context: Operation & Organization - Chiphead Theater
11:55am - 12:35pm: Intuitive Simulation & Measurement Workflow for Hardware Engineers? - Great America K
12:10pm - 12:50pm: Mastering Phase Noise/Jitter Measurements - Great America 2
12:15pm - 1:00pm: Data-Efficient Supervised Machine Learning Technique for Practical PCB Noise Decoupling - Ballroom D
12:15pm - 1:00pm: Designing a Configurable ECU with Python - Ballroom C
12:15pm - 1:00pm: Finite Element Modelling of Copper Foil Loss from AFM Measurements - Ballroom F
12:15pm - 1:00pm: Gallium Nitride vs. Silicon Carbide: Battle of the Wide-Bandgap Semiconductors - Ballroom B
12:15pm - 1:00pm: Mm-Wave Communication Over Dielectric Waveguides: System Design & Applications - Ballroom H
12:15pm - 1:00pm: Optimal Design & Swift Workflow for Multi-Layer Structures - Ballroom E
12:15pm - 1:00pm: Security IP Solutions For A World Of IoT Devices - Great America 1
12:15pm - 1:00pm: The IC-level Conducted Emission Measurement & Simulation Analysis for an Automotive DRAM - Ballroom G
12:30pm - 1:30pm: Panel – Advanced Technologies for Line Card Design - Chiphead Theater
12:30pm - 2:30pm: Conference Networking Lunch - Mission City Ballroom B1
1:45pm - 2:30pm: Maintaining Manufacturing ROI for Engineering Startups - Chiphead Theater
2:00pm - 2:40pm: Far-End Crosstalk In High-Speed PCB Channels - Great America 2
2:00pm - 2:45pm: 224G Connector Solution - Great America J
2:00pm - 2:45pm: 4K eDP Vehicular Display Micro-Coax Cable Designs - Ballroom C
2:00pm - 2:45pm: A Novel Approach to 224 Gb/s Reference Receiver Design Using Raised Cosine Response for Noise Mitigation - Ballroom G
2:00pm - 2:45pm: A Novel Crosstalk Reduction Technique for DDR5 Server Application - Ballroom E
2:00pm - 2:45pm: Accelerating Data Interconnects With PCI Express 6.0 Interface IP - Great America 1
2:00pm - 2:45pm: An Innovative CPU Pin-Field Routing for Signal Integrity Optimization - Ballroom D
2:00pm - 2:45pm: Measurement Bandwidth & Its Impact on Accuracy - Ballroom F
2:00pm - 2:45pm: Micro-LEDs Rise to the Challenge - Ballroom B
2:00pm - 2:45pm: MIMO Crosstalk Cancelation Technique in Serial Electrical Links - Ballroom H
2:40pm - 3:20pm: Physical Layer Validation Challenges of Characterizing 100/200 Gbps/lane Designs - Great America K
2:45pm - 3:00pm: Accurate SI Analysis for PCIe Gen5 Signaling with PCB & Connector Merged Structure up to 50GHz - Chiphead Theater
3:00pm - 3:40pm: Dielectric Permittivity Extraction For Inhomogeneous Dielectric Layers Based On Delta-L & Extended Unterminated Line (EUL) Measurements - Great America 2
3:00pm - 3:45pm: Comprehensive Statistical Analysis of SERDES Links Considering DFE Error Propagation - Ballroom G
3:00pm - 3:45pm: CXL Advances Data Center Performance With Memory Tiering Architecture - Great America 1
3:00pm - 3:45pm: ML-Based AMOP Framework for On-chip Test Sequence Thermal Optimization - Ballroom H
3:00pm - 3:45pm: PCIe 6.0 (PAM4) Signal Integrity Challenges in Immersion-Cooling Datacenters - Ballroom D
3:00pm - 3:45pm: PCIe Gen5, Signal Integrity Implementation Issues & Solutions - Ballroom E
3:00pm - 3:45pm: Pushing the Boundaries of Automotive Connectivity - Ballroom C
3:00pm - 3:45pm: Revolutionary Number Formats for Machine Learning - Ballroom B
3:00pm - 3:45pm: The Influence of EM Field Solver Numerical Solution Space on Measurement Correlation to 50GHz & Beyond - Ballroom F
3:15pm - 4:00pm: Panel – Will AI Ever Replace Engineers? - Chiphead Theater
3:30pm - 4:10pm: IBIS/IBIS-AMI for SerDes and Memory Applications - Great America K
4:00pm - 4:40pm: Improve Power Integrity With Pre-Layout Decoupling Solutions - Great America 2
4:00pm - 5:15pm: Emerging AI Accelerator Architectures - Ballroom B
4:00pm - 5:15pm: Panel – Compute Express Link (CXL) 3.0: Enabling New Usage Models in Composable Disaggregated Infrastructure - Ballroom D
4:00pm - 5:15pm: Panel – Enabling Next Generation Architectures: 224 Gbps Electrical Interfaces - Ballroom G
4:00pm - 5:15pm: Panel – Revolutionizing In-Vehicle PHY Channel Characterization (>10Gbps): Is Simulation the Solution? - Ballroom C
4:00pm - 5:15pm: Panel – What Users Need from Power Integrity Simulators - Ballroom F
4:15pm - 5:00pm: Micro-coax Cable Transfer Performance of High-speed Differential Signals - Chiphead Theater
4:20pm - 5:00pm: Advanced Power Integrity Simulation & Measurement Methods - Great America K
5:00pm - 6:00pm: Booth Bar Crawl - Expo Hall

Thursday, February 2, 2023
8:00am - 8:45am: Addressing Package/PCB Thermal Challenges by Extending Your Power Integrity Analysis Methodology - Great America J
8:00am - 8:45am: Analytical Models for FEC Symbol Error Distribution of DFE Propagation with Precoding and EoBD - Ballroom G
8:00am - 8:45am: Centralized Storage for Next Generation Vehicles: New Standards & Future Roadmaps - Ballroom C
8:00am - 8:45am: Effect of Intra-Pair Skew on Copper Cable Assembly Link Performance - Ballroom E
8:00am - 8:45am: Addressing Package/PCB Thermal Challenges by Extending Your Power Integrity Analysis Methodology - Great America J
8:00am - 8:45am: Analytical Models for FEC Symbol Error Distribution of DFE Propagation with Precoding and EoBD - Ballroom G
8:00am - 8:45am: Centralized Storage for Next Generation Vehicles: New Standards & Future Roadmaps - Ballroom C
8:00am - 8:45am: Effect of Intra-Pair Skew on Copper Cable Assembly Link Performance - Ballroom E
4:00pm - 5:00pm: PCIe Rising: The Journey to 64Gb/s and 128Gb/s - Great America J
4:00pm - 5:15pm: A Simple Method For De-embedding Fixtures Using S-parameter Measurements - Great America K
4:00pm - 5:15pm: Panel – FEC for Next Generation 800G/1.6T Ethernet Systems - Ballroom G
4:00pm - 5:15pm: Panel – PCI Express Specification: A High-Bandwidth, Low-Latency Interface for the Compute Continuum - Ballroom F
4:00pm - 5:15pm: Panel – Photonics Future: Vision, Challenges, and the Path to Infinity & Beyond! - Ballroom D
4:00pm - 5:15pm: Panel – Test on Wheels: Test & Measurement for Automotive Standards - Ballroom C
4:15pm - 5:00pm: Panel - Overcoming Career Challenges for Millenials - Chiphead Theater
5:00pm - 6:00pm: Booth Bar Crawl - Expo Hall

Date: January 31 - February 2, 2023

Hours:
Expo:
Wednesday, February 1, 2023: 11:00am - 6:00pm
Thursday,  February 2 2023: 11:00am - 6:00pm

Conference:
Tuesday, January 31, 2023: 9:00am - 6:00pm
Wednesday, February 1, 2023: 8:00am - 5:15pm
Thursday,  February 2 2023: 8:00am - 5:15pm

Registration:
Tuesday, January 31, 2023: 7:00am - 5:00pm
Wednesday, February 1, 2023: 7:00am - 6:00pm
Thursday, February 2, 2023: 7:00am - 6:00pm

Location: Santa Clara Convention Center - 5001 Great America Parkway Santa Clara, CA 95054

Click here for Registration

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